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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input OR Gate with LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC54/74HCT32A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT32A is identical in pinout to the LS32. * * * * * * Output Drive Capability: 10 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 64 FETs or 16 Equivalent Gates
MC54/74HCT32A
J SUFFIX CERAMIC PACKAGE CASE 632-08
1
14
14 1
N SUFFIX PLASTIC PACKAGE CASE 646-06
14 1
D SUFFIX SOIC PACKAGE CASE 751A-03
ORDERING INFORMATION
LOGIC DIAGRAM
A1 B1 A2 B2 A3 B3 A4 B4 1 3 2 4 6 5 9 8 10 12 11 13 Y4 Y3 Y2 Y=A+B Y1
MC54HCTXXAJ MC74HCTXXAN MC74HCTXXAD
Ceramic Plastic SOIC
PIN ASSIGNMENT
A1 B1 Y1 A2 B2 Y2 GND PIN 14 = VCC PIN 7 = GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC B4 A4 Y4 B3 A3 Y3
FUNCTION TABLE
Inputs A L L H H B L H L H Output Y L H H H
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = 2.4 V, Any One Input 5.5 2.9 2.4 mA Vin = VCC or GND, Other Inputs lout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
MOTOROLA
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS FOR THE MC54/74HCT32A (Voltages Referenced to GND)
MC54/74HCT32A
Symbol
Symbol
Vin, Vout
Symbol
ICC
VOH
VCC
VOL
Vout
Tstg
ICC
ICC
VIH
Iout
VCC
VIL
Vin
PD
TL
tr, tf
Iin
Iin
TA
Additional Quiescent Supply Current
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP) (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Parameter
Parameter
Parameter
Vin = VCC or GND Iout = 0 A
v Vin = VIH or VIL |Iout| v 4.0 mA
Vin = VIH or VIL |Iout| 20 A
v Vin = VIH or VIL |Iout| v 4.0 mA
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 4.5 Value 0 0 50 25 20 260 300 750 500 VCC Volts 5.5 5.5 4.5 4.5 5.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 + 125 VCC Max 500 5.5 - 55 to 25_C 3.98 Min 4.4 5.4 2.0 2.0 Unit Unit mW mA mA mA
_C
_C _C
_C
ns
V
V
V
V
V
0.1
0.26
Max
1.0
0.1 0.1
0.8 0.8
- 55_C
Guaranteed Limits
3.84
Min
4.4 5.4
2.0 2.0
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v 85_C
1.0
0.33
Max
High-Speed CMOS Logic Data DL129 -- Rev 6 0.1 0.1 0.8 0.8 10 25_C to 125_C
v
Min
3.7
4.4 5.4
2.0 2.0
v 125_C
1.0 Max 0.4 0.1 0.1 0.8 0.8
40
v
Unit
A A V V V V
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NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol OUTPUT Y tPLH, tPHL tTLH, tTHL CPD Cin INPUT A OR B Power Dissipation Capacitance (Per Gate)* Maximum Input Capacitance Maximum Output Transition Time, Any Output Maximum Propagation Delay, Input A or B to Output Y tTLH
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS FOR THE MC54/74HCT32A (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Figure 1. Switching Waveforms
1.3 V 10%
1.3 V 10%
tPLH
90%
90%
tr
Parameter
B
A
tf
tPHL
EXPANDED LOGIC DIAGRAM (1/4 OF THE DEVICE)
tTHL
GND
3.0 V
3 Fig. 1, 2 1, 2 - 55 to 25_C Min Typical @ 25C, VCC = 5.0 V Max 10 15 20 Guaranteed Limits Min Y
* Includes all probe and jig capacitance
v 85_C
DEVICE UNDER TEST
15
Figure 2. Test Circuit
Max
10
19
25
MC54/74HCT32A
OUTPUT
Min
v 125_C
TEST POINT
Max
10
22
30
MOTOROLA CL* Unit pF pF ns ns
MC54/74HCT32A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
8
-A14
-B1 7
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 6.23 7.11 3.94 5.08 0.39 0.50 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01
-TSEATING PLANE
K F G D 14 PL 0.25 (0.010) N
M
M
S
TA
J 14 PL 0.25 (0.010)
M
T
B
S
DIM A B C D F G J K L M N
N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
-A-
14 8
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-B-
1 7
P 7 PL
0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C
R X 45
F
SEATING PLANE
D
14 PL
K
M
M B
S
J
0.25 (0.010)
T
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HCT32A
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
5
*MC54/74HCT32A/D*
MC54/74HCT32A/D MOTOROLA

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